1. Field of the Invention
The present invention relates to a data processor like a microprocessor (MPU), and in particular, to a method of processing simultaneous execution of two instructions in a 32-bit reduced instruction set computer (RISC) processor.
2. Description of the Related Art
Known examples related to the present invention have been described in pages A-39 and A-58 of the "MIPS RISC Architechture", Prentice-Hall Ltd. (1988), in pages 54 to 55 of the "Digest of Technical Papers" of the 1989 IEEE International Solid-State Circuit Conference, and in pages 199 to 209 of an article entitled "Microprocessor 80860 Including One Million Transistors Integrated Therein For Scientific Computations And Visualization", Nikkei-Electronics, Apr. 3, 1989 (No. 470).
Recently, the reduced instruction set computer (RISC) architecture has been employed in a processor system having a high performance. In such a RISC processor system, the instruction code length is fixed to 32 bits. Consequently, when 32-bit immediate data are to be operated, an operation thereon is required to be achieved with two instructions, for example, as follows. EQU LUI rt, &lt;upper 16 bits&gt; EQU ORI rt,rt, &lt;lower 16 bits&gt;
The first instruction here is a load upper immediate instruction, which shifts to the left-hand side by 16 bits 16-bit immediate data specified therein to attain 32-bit data, thereby storing the 32-bit data in a t-th register rt.
The second instruction is an or immediate instruction, which adds 16-bit 0s to the upper portion the 16-bit immediate data specified therein to compute an OR operation between the resultant data and the content of the t-th register rt, thereby storing a result of the OR operation in the register rt.
When these two instructions are executed, the register rt is loaded with the 32-bit immediate data.
Specifications of a processor of this kind have been described in the architecture manual of the 32-bit microprocessor R2000 published from the MIPS Computer Systems Inc.